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19-5182; Rev 0; 3/10
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TION KIT EVALUA BLE AVAILA
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
General Description
The MAX3946 is a +3.3V, multirate, low-power laser diode driver designed for Ethernet and Fibre Channel transmission systems at data rates up to 11.3Gbps. This device is optimized to drive a differential transmitter optical subassembly (TOSA) with a 25I flex circuit. The unique design of the output stage enables use of unmatched TOSAs, greatly reducing headroom limitations and lowering power consumption. The device receives differential CML-compatible signals with on-chip line termination. It can deliver laser modulation current of up to 80mA, at an edge speed of 20ps (20% to 80%), into a 5I to 25I external differential load. The device is designed to have a symmetrical output stage with on-chip back terminations integrated into its outputs. A high-bandwidth, fully differential signal path is implemented to minimize deterministic jitter. An equalization block can be activated to compensate for the SFP+ connector. The integrated bias circuit provides programmable laser bias current up to 80mA. Both the laser bias generator and the laser modulator can be disabled from a single pin, DISABLE. A 3-wire digital interface reduces the pin count and permits adjustment of input equalization, pulse-width adjustment, Tx polarity, Tx deemphasis, modulation current, and bias current without the need for external components. The MAX3946 is available in a 4mm x 4mm, 24-pin TQFN package. Modules
S Up to 100mW Power Consumption Reduction by
Features
S 225mW Power Dissipation Enables < 1W SFP+
MAX3946
Enabling the Use of Unmatched FP/DFB TOSAs
S Supports SFF-8431 SFP+ MSA and SFF-8472
Digital Diagnostic
S 225mW Power Dissipation at 3.3V (IMOD = 40mA,
IBIAS = 60mA Assuming 25I TOSA)
S Single +3.3V Power Supply S Up to 11.3Gbps (NRZ) Operation S Programmable Modulation Current from 10mA to
100mA (5I Load)
S Programmable Bias Current from 5mA to 80mA S Programmable Input Equalization S Programmable Output Deemphasis S 25I Output Back Termination at TOUT+ and
TOUTS DJ Performance 7psP-P with Mismatched
Differential Load (5I)
S DJ Performance 5psP-P with Mismatched
Differential Load (25I)
S DJ Performance 5psP-P with 50I Differential Load S Programmable Pulse Width S Edge Transition Times of 20ps S Bias Current Monitor S Integrated Eye Safety Features S 3-Wire Digital Interface S -40C to +95C Operation
Applications
4x/8x FC SFP+ Optical Transceivers 10GFC SFP+ Optical Transceivers 10GBASE-LR SFP+ Optical Transceivers 10GBASE-LRM SFP+ Optical Transceivers OC192-SR XFP/SFP+ Transceivers
Ordering Information
PART MAX3946ETG+ TEMP RANGE -40C to +85C PIN-PACKAGE 24 TQFN-EP*
Note: Parts are guaranteed by design and characterization to operate over the -40C to +95C ambient temperature range (TA) and are tested up to +85C. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
ABSOLUTE MAXIMUM RATINGS
VCC, VCCT, VCCD ................................................-0.3V to +4.0V Current Into TOUT+ and TOUT-.................................... +100mA Current Into TIN+ and TIN- ............................. -20mA to +20mA Voltage Range at TIN+, TIN-, DISABLE, SDA, SCL, CSEL, FAULT, BMAX, BMON, and BIAS ...................... -0.3V to (VCC + 0.3V) Voltage Range at BIAS........................................................-0.3V to VCC Voltage Range at TOUT+ and TOUT- ....(VCC - 1.3V) to (VCC + 1.3V) Current into BIAS.........................................................................+130mA Continuous Power Dissipation (TA = +70NC) 24-Pin TQFN (derate 27.8mW/NC above +70NC) .......2222mW Storage Temperature Range .......................... -55NC to +150NC Die Attach Temperature .................................................+400NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER POWER SUPPLY Power-Supply Current Power-Supply Voltage Power-Supply Noise POWER-ON RESET VCC for Enable High VCC for Enable Low DATA INPUT SPECIFICATION Input Data Rate Differential Input Voltage Differential Input Resistance Differential Input Return Loss Common-Mode Input Return Loss BIAS GENERATOR Maximum Bias Current Minimum Bias Current IBIASMAX IBIASMIN Current into BIAS pin, DISABLE = low, and TX_EN = high Current into BIAS pin, DISABLE = low, and TX_EN = high Current into BIAS pin, DISABLE = high or TX_EN = low or SET_BIAS = H0x00; BIAS pin voltage at VCC 80 5 mA mA VIN RIN SDD11 SCC11 Part powered on, f P 10GHz Part powered on, 1GHz P f P 10GHz TXEQ_EN = high, launch amplitude into FR4 transmission line P 5.5in TXEQ_EN = low 1 0.19 0.15 75 100 12 10 10 11.3 0.7 1.0 125 I dB dB Gbps VP-P 2.3 2.55 2.45 2.75 V V ICC VCC DC to 10MHz 10MHz to 20MHz Excludes output current through the external pullup inductors (Note 2) 2.85 68 90 3.63 100 10 mA V mVP-P SYMBOL CONDITIONS MIN TYP MAX UNITS
Bias-Off Current
IBIAS-OFF
100
FA
2
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Bias Current DAC Stability Instantaneous Compliance Voltage at BIAS BMON Current Gain Compliance Voltage at BMON BMON Current Gain Stability LASER MODULATOR TOUT+ and TOUTInstantaneous Output Compliance Voltage Current into external 25I differential termination, output common-mode voltage = VCC Current into external 50I differential termination, output common-mode voltage = VCC VCC 1.0 VCC + 1.0 V 5mA P IBIAS P 80mA (Notes 1, 3) VBIAS GBMON GBMON = IBMON/IBIAS, external resistor to ground defines voltage SYMBOL CONDITIONS 5mA P IBIAS P 80mA, VBIAS = VCC - 1.5V (Notes 1, 3) 0.9 9 0 1.2 MIN TYP 1 1.5 10 MAX 3 2.1 11 1.8 4 UNITS % V mA/A V %
MAX3946
80 mAP-P 60 10 50 mAP-P I 100 1.5 22 22 5 5 7 5 0.19 8 6 10.5 0.55 psRMS dB 3 30 30 12 12 psP-P ps FA %
Maximum Modulation Current
IMODMAX
Minimum Modulation Current Differential Output Resistance Modulation-Off Maximum Current Modulation Current DAC Stability Modulation Current Edge Speed (Note 1)
IMODMIN 2 x ROUT IMOD-OFF Current between TOUT+ and TOUT- when DISABLE = high or TX_EN = low or SET_IMOD = H0x00 10mA P IMOD P 80mA (Notes 1, 3) 20% to 80%, 20mA P IMOD P 80mA tR, tF 20% to 80%, 10mA P IMOD P 80mA, TXDE_MD[1:0] = 3d 10mA P IMOD P 60mA, 11.3Gbps, output differential load = 50I 10mA P IMOD P 80mA, 11.3Gbps, output differential load = 25I 10mA P IMOD P 80mA, 11.3Gbps, output differential load = 5I 10mA P IMOD P 60mA, 10.7Gbps, output differential load = 50I (K28.5 pattern)
Deterministic Jitter (Notes 1, 4)
DJ
Random Jitter Differential Output Return Loss
RJ SDD22
10mA P IMOD P 80mA, output differential load = 25I (Note 1) Part powered on, f P 5GHz Part powered on, f P 10GHz
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SAFETY FEATURES Threshold Voltage at BMAX VBMAX FAULT always occurs for VBMAX R 1.3, FAULT never occurs for VBMAX < 1.1 (Note 1, Figure 1) FAULT never occurs for VBIAS R 0.57, FAULT always occurs for VBIAS < 0.44 Warning always occurs for VBMON R VCC - 0.5V, warning never occurs for VBMON < VCC - 0.7V Time from rising edge of DISABLE input signal to IBIAS < IBIAS-OFF and IMOD < IMOD-OFF Time from falling edge of DISABLE to IBIAS and IMOD at 90% of steady state Time from power-on or negation of FAULT using DISABLE Time from fault to FAULT on, CFAULT P 20pF, RFAULT = 4.7kI Time DISABLE must be held high to reset FAULT IBIAS-FS INL DNL SET_IBIAS[8:1] = HxFF 5mA P IBIAS P 80mA 5mA P IBIAS P 80mA, guaranteed monotonic at 8-bit resolution SET_IBIAS[8:1] 0.5 1.1 1.2 1.3 V SYMBOL CONDITIONS MIN TYP MAX UNITS
Threshold Voltage at BIAS
VBIAS
0.44 VCC 0.7
0.48 VCC 0.6
0.57 VCC 0.5
V
Threshold Voltage at BMON SFP TIMING REQUIREMENTS DISABLE Assert Time
VBMON
V
t_OFF
0.05
1
Fs
DISABLE Negate Time FAULT Reset Time of Power-On Time FAULT Reset Time DISABLE to Reset BIAS CURRENT DAC Full-Scale Current LSB Size Integral Nonlinearity Differential Nonlinearity
t_ON t_INIT t_FAULT
0.5 50 0.5
5 200 2
Fs Fs Fs Fs
80
100 190 0.5 0.5
mA FA %FS LSB
MODULATION CURRENT DAC (25I DIFFERENTIAL LOAD) Full-Scale Current LSB Size Integral Nonlinearity Differential Nonlinearity CONTROL I/O SPECIFICATIONS DISABLE Input Current DISABLE Input High Voltage DISABLE Input Low Voltage 4 IIH IIL VIH VIL Depends on pullup resistance 1.8 0 500 12 800 VCC 0.8 FA V V INL DNL 10mA P IMOD P 80mA 10mA P IMOD P 80mA, guaranteed monotonic at 9-bit resolution SET_IMOD[8:0] IMOD-FS SET_IMOD[8:1] = HxFF 80 105 200 Q1 Q0.5 mA FA %FS LSB
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER DISABLE Input Resistance Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Output High Voltage Output Low Voltage SCL Clock Frequency SCL Pulse-Width High SCL Pulse-Width Low SDA Setup Time SDA Hold Time SCL Rise to SDA Propagation Time CSEL Pulse-Width Low CSEL Leading Time Before the First SCL Edge CSEL Trailing Time After the Last SCL Edge SDA, SCL Load SYMBOL RPULL VIH VIL VHYST IIL, IIH VOH VOL fSCL tCH tCL tDS tDH tD tCSW tL tT CB Total bus capacitance on one line with 4.7kI pullup to VCC 500 500 500 20 0.5 0.5 100 100 5 VIN = 0V or VCC, internal pullup or pulldown is 75kI typical External pullup is (4.7kI to 10kI) to VCC External pullup is (4.7kI to 10kI) to VCC VCC - 0.5 0.4 400 1000 80 150 CONDITIONS Internal pullup resistor MIN 4.7 2.0 TYP 7.5 MAX 10 VCC 0.8 UNITS kI V V mV FA V V kHz Fs Fs ns ns ns ns ns ns pF
MAX3946
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, SCL, CSEL)
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (Figure 5)
Note 1: Guaranteed by design and characterization (TA = -40NC to +95NC). Note 2: BIAS is connected to 2.0V. TOUT+/TOUT- are connected through pullup inductors to a separate supply that is equal to VCCT. ICC = 4.92 + 0.0383 x IBIAS + 0.3692 x IMOD Note 3: Stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC = VCCREF Q5%. VCCREF = 3.0V to 3.45V. Reference current measured at VCCREF, TA = +25NC. Note 4: Measured with K28.5 data pattern at 10.7Gbps and with a (27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) + 72 ones) pattern at 11.3Gbps.
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
VCCD 0.01F
VCC + 4.7kI VCC 2.0V VCCT 0.01F VCCD BIAS CSEL VCCT SCL SDA 0.1F
VEET VCC VCC 0.01F
VCCT
0.01F Z0 = 50I 0.01F Z0 = 50I VCC 0.01F VEET VCCD VCCT FAULT BMON BMAX VCCT TINVCC TOUTEP 25I TIN+
35I
0.1F 50I
MAX3946
TOUT+
25I 75I
SAMPLING OSCILLOSCOPE
0.1F 50I
35I 50I 50I
DISABLE
VCC 4.7kI 0.01F 1kI 0.01F 0.1F
VCCT
1kI
Figure 1. AC Test Setup
6
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
(VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) +72 ones, unless otherwise noted.)
Typical Operating Characteristics
MAX3946
10.3Gbps OPTICAL EYE DIAGRAM
MAX3946 toc01
10.3Gbps ELECTRICAL EYE DIAGRAM
223 - 1 PRBS 50 LOAD
MAX3946 toc02
20ps/div
INPUT DIFFERENTIAL RETURN LOSS vs. FREQUENCY
MAX3946 toc03
INPUT COMMON-MODE RETURN LOSS vs. FREQUENCY
MAX3946 toc04
INPUT DIFFERENTIAL TO COMMON-MODE RETURN LOSS vs. FREQUENCY
MAX3946 toc05
0 -5 -10 SDD11 (dB)
0 -5 -10 SCC11 (dB)
0 -10 SCD11 (dB) -20 -30 -40 -50
-15 -20 -25 -30 -35 100 1000 10,000 100,000 FREQUENCY (MHz)
-15 -20 -25 -30 -35 1000 10,000 FREQUENCY (MHz) 100,000
100
1000
10,000
100,000
FREQUENCY (MHz)
OUTPUT DIFFERENTIAL RETURN LOSS vs. FREQUENCY
MAX3946 toc06
OUTPUT COMMON-MODE RETURN LOSS vs. FREQUENCY
MAX3946 toc07
RANDOM JITTER vs. MODULATION CURRENT (AT LOAD)
0.9 0.8 0.7 RJ (psRMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 70 80 MODULATION CURRENT (mAP-P)
-5 -10 SDD22 (dB) -15 -20 -25 -30 -35 100 1000 10,000
-5 -10 SCC22 (dB) -15 -20 -25 -30 -35
11.3Gbps, 25 DIFFERENTIAL LOAD 1111 0000 PATTERN
100,000
100
1000
10,000
100,000
FREQUENCY (MHz)
FREQUENCY (MHz)
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MAX3946 toc08
0
0
1.0
7
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
(VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) +72 ones, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (IMOD = 40mAP-P, IBIAS = 60mA)
MAX3946 toc09
Typical Operating Characteristics (continued)
TOTAL CURRENT vs. TEMPERATURE (IMOD AT LOAD = 40mAP-P, IBIAS = 60mA)
MAX3946 toc10
EYE CROSSING PERCENT vs. SET_PWCTRL
70 65 60 CROSSING (%) 55 50 45 40 35 30 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 SET_PWCTRL[3:0] 25
MAX3946 toc11
100 90 SUPPLY CURRENT (mA) 80 70 60 50
CURRENT INTO VCC, VCCT, AND VCCD PINS
220 210 SUPPLY CURRENT (mA) 200 190 180 170 160 150 140
CURRENT INTO VCC, VCCT, AND VCCD PINS PLUS MODULATION AND BIAS CURRENT
75
25 LOAD ITOTAL (25 LOAD) = 45.8 + 1.038 x IBIAS + 2.08 x IMOD
5 LOAD ITOTAL (5 LOAD) = 45.8 + 1.038 x IBIAS + 1.57 x IMOD
-40 -25 -10 5 20 35 50 65 80 95
-40 -25 -10
5
20
35
50
65
80
95
TEMPERATURE (C)
TEMPERATURE (C)
BIAS CURRENT vs. DAC SETTING
MAX3946 toc12
MODULATION CURRENT (AT LOAD) vs. DAC SETTING
MAX3946 toc13
MODULATION CURRENT DEEMPHASIS vs. MANUAL DEEMPHASIS SETTING
9 8 DEEMPHASIS (%) 7 6 5 4 3 2 1 0
MODULATION CURRENT (mAP-P)
100 BIAS CURRENT (mA) 80 60 40 20 0 0 200 400
80 70 60 50 40 30 20 10 0
RLOAD = 25 DIFFERENTIAL
SET_IMOD[8:0] = 230d TXDE_MD[1:0] = 2d
RLOAD = 50 DIFFERENTIAL
600
0
200
400
600
10
20
30
40
SET_IBIAS[8:0]
SET_IMOD[8:0]
SET_TXDE[5:0]
BIAS MONITOR CURRENT vs. TEMPERATURE
MAX3946 toc15
TRANSITION TIME vs. MODULATION CURRENT
MAX3946 toc16
TRANSITION TIME vs. DEEMPHASIS SETTING
SET_IMOD[8:0] = 230d 25 LOAD, 20% TO 80% 10Gbps, 1111 0000 PATTERN
MAX3946 toc17
700 600 BMON CURRENT (A) 500 400 300 200 100 0 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C)
40 35 TRANSITION TIME (ps) 30 25 20 15 10 0
25 LOAD, 20% TO 80% 10Gbps, 11111 00000 PATTERN
40 35 TRANSITION TIME (ps) 30 25 20
IBIAS = 60mA IBIAS = 30mA
FALL TIME
FALL TIME
IBIAS = 10mA
RISE TIME
RISE TIME
15 10 10 20 30 40 SET_TXDE[5:0]
20
40
60
80
100
IMOD (mA)
8
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MAX3946 toc14
120
90
10
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
(VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) +72 ones, unless otherwise noted.)
Typical Operating Characteristics (continued)
MAX3946
TRANSMITTER DISABLE
VCC
MAX3946 toc18
TRANSMITTER ENABLE
VCC
MAX3946 toc19
RESPONSE TO FAULT
VBIAS
MAX3946 toc20
3.3V
3.3V t_ON = 600ns
EXTERNAL FAULT
FAULT DISABLE
LOW
FAULT
LOW HIGH
FAULT
HIGH
HIGH LOW
DISABLE OUTPUT
LOW
DISABLE
LOW
OUTPUT 100ns/div 1s/div
OUTPUT 1s/div
FAULT RECOVERY
VBIAS
MAX3946 toc21
FREQUENT ASSERTION OF DISABLE
VBIAS
MAX3946 toc22
EXTERNAL FAULT
EXTERNAL FAULT REMOVED LOW HIGH LOW
FAULT
FAULT
HIGH LOW HIGH LOW
DISABLE
DISABLE
OUTPUT 4s/div
OUTPUT 4s/div
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Pin Configuration
CSEL VCCD VCCT 13 12 11 10 VCCT TOUT+ TOUT+ TOUTTOUTVCCT 9 *EP 8 7 1 VCCD 2 DISABLE 3 FAULT 4 BMAX 5 BMON 6 VCCT BIAS 14 SDA 17 SCL 18 VEET 19 VCC 20 TIN+ 21 TIN- 22 VCC 23 VEET 24
TOP VIEW
16
15
MAX3946 +
THIN QFN (4mm x 4mm)
*EXPOSED PAD CONNECTED TO GROUND.
Pin Description
PIN 1, 15 2 NAME VCCD DISABLE FUNCTION Power Supply. Provides supply voltage to the digital block. Disable Input, CMOS Input. Set to logic-low for normal operation. Logic-high or open disables both the modulation current and the bias current. Internally pulled up by a 7.5kI resistor to VCC. Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the fault condition has been removed. A logic-low occurs when the fault condition has been removed and the fault latch has been cleared by toggling the DISABLE pin. FAULT should be pulled up to VCC by a 4.7kI to 10kI resistor. Analog Laser Bias-Current Limit. A resistive voltage-divider connected among BMON, BMAX, and ground sets the maximum allowed laser bias current limit. The voltage at BMAX is internally compared to 1.2V bandgap reference voltage. Bias Current-Monitor Output. Current out of this pin develops a ground-referenced voltage across external resistor(s) that is proportional to the laser bias current. The current sourced by this pin is typically 1/100th the BIAS pin current. Power Supply. Provides supply voltage to the output block. Inverted Modulation Current Output. Internally pulled up by a 25I resistor to VCCT. Noninverted Modulation Current Output. Internally pulled up by a 25I resistor to VCCT. Laser Bias Current Connection Chip-Select Input, CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends the cycle and resets the control state machine. Internally pulled down by a 75kI resistor to ground. Serial-Data Bidirectional Input, CMOS. Open-drain output. This pin has a 75kI internal pullup, but it requires an external 4.7kI to 10kI pullup resistor. (Data line-collision protection is implemented.)
3
FAULT
4
BMAX
5 6, 7, 12, 13 8, 9 10, 11 14 16 17
BMON VCCT TOUTTOUT+ BIAS CSEL SDA
10
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
Pin Description (continued)
PIN 18 19, 24 20, 23 21 22 -- NAME SCL VEET VCC TIN+ TINEP Ground Power-Supply Connections. Provides supply voltage to the core circuitry. Noninverted Data Input Inverted Data Input Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical performance (see the Exposed-Pad Package and Thermal Considerations section). FUNCTION Serial-Clock Input, CMOS. This pin has 75kI internal pulldown.
MAX3946
VCCD 7.5kI
DISABLE FAULT BMAX
VCM
TOUT+ TX_EN EYE SAFETY AND OUTPUT CONTROL LASER BIAS CURRENT LIMITER POWER-ON RESET 25I TOUT25I VCCT
50I TIN+ TIN-
50I
TX_POL 1 0 PW CONTROL
VCC IBIAS IBIAS 100
EQ
BIAS
IMOD_DAC + IDE_DAC
VCCD 75kI CONTROL LOGIC
BMON
SDA SCL CSEL
75kI 3-WIRE INTERFACE REGISTER
75kI
SET_TXEQ SET_PWCTRL 9b DAC SET_IMOD 6b DAC SET_TXDE 9b DAC SET_IBIAS
MAX3946
Figure 2. Functional Diagram ______________________________________________________________________________________ 11
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Detailed Description
The MAX3946 SFP+ laser driver is designed to drive 5I to 50I lasers from 1Gbps to 11.3Gbps. The device contains an input buffer with programmable equalization, pulse-width adjustment, bias current and modulation current DACs, output driver with programmable deemphasis, power-on reset circuitry, bias monitor, laser current limiter, and eye-safety circuitry. A 3-wire digital interface is used to control the transmitter functions. The registers that control the device's functionality are TXCTRL, SET_IMOD, SET_IBIAS, IMODMAX, IBIASMAX, MODINC, BIASINC, SET_TXEQ, SET_PWCTRL, and SET_TXDE. the initialization procedure after POR. The LSB (bit 0) of SET_IBIAS is initialized to zero after POR and can be updated using the BIASINC register. The IBIASMAX register should be programmed to a desired maximum bias current value (up to 96mA) to protect the laser. The IBIASMAX register limits the maximum SET_IBIAS[8:1] DAC code. After initialization the value of the SET_IBIAS DAC register should be updated using the BIASINC register to optimize cycle time and enhance laser safety. The BIASINC register is an 8-bit register where the first 5 bits contain the increment information in two's complement notation. Increment values range from -8 to +7 LSBs. If the updated value of SET_IBIAS[8:1] exceeds IBIASMAX[7:0], the IBIASERR warning flag is set and SET_IBIAS[8:0] remains unchanged. The modulation current from the device is optimized to provide up to 80mA of modulation current into a 5I to 25I differential laser load (60mA for 50I laser load) with 300FA to 200FA resolution. The modulation current is controlled through the 3-wire digital interface using the SET_IMOD, IMODMAX, MODINC, and SET_TXDE registers. For laser operation, the laser modulation current can be set using the 9-bit SET_IMOD DAC. The upper 8 bits are set by the SET_IMOD[8:1] register, commonly used during the initialization procedure after POR. The LSB (bit 0) of SET_IMOD is initialized to zero after POR and can be updated using the MODINC register. The IMODMAX register should be programmed to a desired maximum modulation current value (up to 96mA) to protect the laser. The IMODMAX register limits the maximum SET_IMOD[8:1] DAC code.
The input is internally biased and terminated with 50I to a common-mode voltage. The first amplifier stage features a programmable equalizer for high-frequency losses including SFP connector. Equalization is controlled by the SET_TXEQ register and TXEQ_EN bit, TXCTRL[3] (Table 1). The TX_POL bit in the TXCTRL register controls the polarity of TOUT+ and TOUT- vs. TIN+ and TIN-. The SET_PWCTRL register controls the output eye crossing (Table 5). A status indicator bit (TXED) monitors the presence of an AC input signal. The device's bias current is optimized to provide up to 80mA of bias current into a 5I to 50I laser load with 200FA resolution. The bias current is controlled through the 3-wire digital interface using the SET_IBIAS, IBIASMAX, and BIASINC registers. For laser operation, the laser bias current can be set using the 9-bit SET_IBIAS DAC. The upper 8 bits are set by the SET_IBIAS[8:1] register, commonly used during
Input Buffer with Programmable Equalization
Modulation Current DAC
Bias Current DAC
Table 1. Input Equalization Control Register Settings
TXCTRL[3] TXEQ_EN 0 1 1 1 1 SET_TXEQ[2:1] X 0 0 1 1 X 0 1 0 1 DESCRIPTION 150mVP-P to 1000mVP-P differential input amplitude (default setting) Optimized for 1in to 4in FR4, 190mVP-P to 450mVP-P differential launch amplitude from source Optimized for 4in to 6in FR4, 190mVP-P to 450mVP-P differential launch amplitude from source Optimized for 1in to 4in FR4, 450mVP-P to 700mVP-P differential launch amplitude from source Optimized for 4in to 6in FR4, 450mVP-P to 700mVP-P differential launch amplitude from source
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
VCC BIAS
IBIAS 100
MAX3946
0.6V
+ -
WARNING
OR BMON 100kI BMAX R1
IF BMAX IS NOT USED
OR
IF BMON IS NOT USED
OR
IF BMAX AND BMON ARE NOT USED
R1
1kI
FAULT 1.2V R2 1kI R2
Figure 3. BMON and BMAX Circuitry
After initialization the value of the SET_IMOD DAC register should be updated using the MODINC register to optimize cycle time and enhance laser safety. The MODINC register is an 8-bit register where the first 5 bits contain the increment information in two's complement notation. Increment values range from -8 to +7 LSBs. If the updated value of SET_IMOD[8:1] exceeds IMODMAX[7:0], the IMODERR warning flag is set and SET_IMOD[8:0] remains unchanged. Modulation current sent to the laser is actually the combination of the current generated by the SET_IMOD register and current subtracted from this by the SET_TXDE register. The output driver is optimized for a 5I to 50I differential load. The output stage also features programmable deemphasis that can be set as a percentage of the modulation current. The deemphasis function is controlled by the TXDE_MD[1] and TXDE_MD[0] bits (TXCTRL[5:4]) and SET_TXDE[5:0]. POR ensures that the laser is off until supply voltage has reached a specified threshold (2.75V). After POR, bias current and modulation current ramps are controlled to avoid overshoot. In the case of a POR, all registers are reset to their default values.
Current out of the BMON pin is typically 1/100th the value of the current at the BIAS pin. The total resistance to ground at BMON sets the voltage gain. An internal comparator at the BMAX pin latches a fault if the voltage on BMAX exceeds the value of 1.2V. The BMAX voltagesense pin is connected by means of a voltage-divider to the BMON pin and ground. The full-scale range of the BMON voltage is 1.2V x (R1/R2 + 1) (Figure 3). The analog bias-current limit is determined by (1.2V/R2) x 100. The safety and output control circuitry includes the disable pin (DISABLE) and disable bit (TX_EN), along with a fault indicator and fault detectors (Figure 4). The device has two types of faults, HARD FAULT and SOFT FAULT. A HARD FAULT triggers the FAULT pin, and the output to the laser is disabled. A SOFT FAULT operates as a warning, and the outputs are not disabled. Both types of faults are stored in the TXSTAT1 and TXSTAT2 registers. The FAULT pin is a latched output that can be cleared by toggling the DISABLE pin. Toggling the DISABLE pin also clears the TXSTAT1 and TXSTAT2 registers. A single-point fault can be a short to VCC or ground. Table 2 shows the circuit response to various singlepoint failures.
BMON and BMAX Functions
Eye Safety and Output Control Circuitry
Output Driver
Power-On Reset (POR)
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
VCC FAULT REGISTERS
TOUTTOUT+
<0> FAULT IMOD 0.44V BIAS VCC - 2V <1>
<2> FAULT REGISTER TXSTAT1 <3>
IBIAS BMAX
VCC - 1.3V
ADDR = H0x06
1.3V IBIAS 100 <4>
UNUSED
<5>
BMON VCC - 0.5V POR VCC 7.5kI DISABLE 2.3V
<6>
<7> RESET
UNUSED LOSS-OF-SIGNAL CIRCUIT
WARNING REGISTER TXSTAT2 <0> ADDR = H0x07 <1>
SET_IBIAS IBIASMAX SET_IMOD IMODMAX
<2>
<3>
Figure 4. Eye Safety Circuitry 14 _____________________________________________________________________________________
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
Table 2. Circuit Response to Single-Point Faults
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME VCCD DISABLE FAULT BMAX BMON VCCT VCCT TOUTTOUTTOUT+ TOUT+ VCCT VCCT BIAS VCCD CSEL SDA SCL VEET VCC TIN+ TINVCC VEET SHORT TO VCC Normal Disabled Normal (Note 1) Disabled--HARD FAULT Disabled--HARD FAULT Normal Normal IMOD is reduced IMOD is reduced IMOD is reduced IMOD is reduced Normal Normal IBIAS is on--No fault Normal Normal (Note 1) Normal (Note 1) Normal (Note 1) Disabled--Fault (external supply shorted) (Note 2) Normal SOFT FAULT SOFT FAULT Normal Disabled--Fault (external supply shorted) (Note 2) SHORT TO GROUND Disabled--HARD FAULT Normal (Note 1). Can only be disabled by other means. Normal (Note 1) Normal (Note 1) Normal (Note 1) Disabled--Fault (external supply shorted) (Note 2) Disabled--Fault (external supply shorted) (Note 2) Disabled--HARD FAULT Disabled--HARD FAULT Disabled--HARD FAULT Disabled--HARD FAULT Disabled--Fault (external supply shorted) (Note 2) Disabled--Fault (external supply shorted) (Note 2) Disabled--HARD FAULT Disabled--Fault (external supply shorted) (Note 2) Normal (Note 1) Normal (Note 1) Normal (Note 1) Normal Disabled--HARD FAULT (external supply shorted) (Note 2) SOFT FAULT SOFT FAULT Disabled--HARD FAULT (external supply shorted) (Note 2) Normal OPEN Normal (Note 3)--Redundant path Disabled Normal (Note 1) Disabled--HARD FAULT Disabled--HARD FAULT Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path IMOD is reduced IMOD is reduced IMOD is reduced IMOD is reduced Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path Disabled--HARD FAULT Normal (Note 3)--Redundant path Normal (Note 1) Normal (Note 1) Normal (Note 1) Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path Normal (Note 1) Normal (Note 1) Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path
MAX3946
15
Note 1: Normal--Does not affect laser power. Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device), and the main supply is collapsed by the short. Note 3: Normal in functionality, but performance could be affected. Warning: Shorted to VCC or shorted to ground on some pins can violate the Absolute Maximum Ratings.
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
The device implements a proprietary 3-wire digital interface. An external controller generates the clock. The 3-wire interface consists of an SDA bidirectional data line, an SCL clock signal input, and a CSEL chip-select input (active high). The external master initiates a data transfer by asserting the CSEL pin. The master starts to generate a clock signal after the CSEL pin has been set to a logic-high. All data transfers are most significant bit (MSB) first. Protocol Each operation consists of 16-bit transfers (15-bit address/data, 1-bit RWN). The bus master generates 16 clock cycles to SCL. All operations transfer 8 bits to the device. The RWN bit determines if the cycle is read or write. See Table 3. Register Addresses The device contains 13 registers available for programming. Table 4 shows the registers and addresses. Write Mode (RWN = 0) The master generates 16 total clock cycles at SCL. The master outputs a total of 16 bits (MSB first) to the SDA line at the falling edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 5 shows the interface timing.
3-Wire Interface
Read Mode (RWN = 1) The master generates 16 total clock cycles at SCL. The master outputs a total of 8 bits (MSB first) to the SDA line at the falling edge of the clock. The SDA line is released after the RWN bit has been transmitted. The slave outputs 8 bits of data (MSB first) at the rising edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 5 shows the interface timing. Mode Control Normal mode allows read-only instruction for all registers except MODINC and BIASINC. The MODINC and BIASINC registers can be updated during normal mode. Doing so speeds up the laser control update through the 3-wire interface by a factor of two. The normal mode is the default mode. Setup mode allows the master to write unrestricted data into any register except the status (TXSTAT1, TXSTAT2) registers. To enter the setup mode, the MODECTRL register (address = H0x0E) must be set to H0x12. After the MODECTRL register has been set to H0x12, the next operation is unrestricted. The setup mode is automatically exited after the next operation is finished. This sequence must be repeated if further unrestricted settings are necessary.
Table 3. Digital Communication Word Structure
BIT 15 14 13 12 11 10 9 8 RWN 7 6 5 4 3 2 1 0 Register Address Data that is written or read
Table 4. Register Descriptions and Addresses
ADDRESS H0x05 H0x06 H0x07 H0x08 H0x09 H0x0A H0x0B H0x0C H0x0D H0x0E H0x0F H0x10 H0x11 16 NAME TXCTRL TXSTAT1 TXSTAT2 SET_IBIAS SET_IMOD IMODMAX IBIASMAX MODINC BIASINC MODECTRL SET_PWCTRL SET_TXDE SET_TXEQ Transmitter Control Register Transmitter Status Register 1 Transmitter Status Register 2 Bias Current Setting Register Modulation Current Setting Register Maximum Modulation Current Setting Register Maximum Bias Current Setting Register Modulation Current Increment Setting Register Bias Current Increment Setting Register Mode Control Register Pulse-Width Control Register Deemphasis Control Register Equalization Control Register FUNCTION
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
WRITE MODE CSEL SCL SDA A6 tL tCH 0 tCL 1 tDS A5 A4 A3 tDH READ MODE CSEL SCL SDA A6 tL tCH 0 tT tCL 1 tDS A5 A4 A3 tDH A2 A1 A0 RWN D7 D6 2 3 4 5 6 7 8 9 tD D5 D4 D3 D2 D1 D0 10 11 12 13 14 15 A2 A1 A0 RWN D7 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tT
Figure 5. Timing for 3-Wire Digital Interface
Transmitter Control Register (TXCTRL)
Bit # Name Default Value 7 X X 6 X X 5 0 4 0 3 TXEQ_EN 0 2 SOFTRES 0 1 TX_POL 1 0 TX_EN 1 ADDRESS H0x05 TXDE_MD[1] TXDE_MD[0]
Bits 5 and 4: TXDE_MD[1:0]. Controls the mode of the transmit output deemphasis circuitry. 00 = deemphasis is fixed at 6.25% of the modulation amplitude 01 = deemphasis is fixed at 3.125% of the modulation amplitude 10 = deemphasis is programmed by the SET_TXDE register setting 11 = deemphasis is at its maximum of approximately 9% Bit 3: TXEQ_EN. Enables or disables the input equalization circuitry. 0 = disabled 1 = enabled Bit 2: SOFTRES. Resets all registers to their default values. 0 = normal 1 = reset Bit 1: TX_POL. Controls the polarity of the signal path. 0 = inverse 1 = normal Bit 0: TX_EN. Enables or disables the output circuitry. 0 = disabled 1 = enabled
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Transmitter Status Register 1 (TXSTAT1)
Bit # Name Default Value 7 (STICKY) FST[7] X 6 (STICKY) FST[6] X 5 (STICKY) X X 4 (STICKY) FST[4] X 3 (STICKY) FST[3] X 2 (STICKY) FST[2] X 1 (STICKY) FST[1] X 0 (STICKY) TX_FAULT X ADDRESS H0x06
Bit 7: FST[7]. When the VCCT supply voltage is below 2.3V, the POR circuitry reports a fault. Once the VCCT supply voltage is above 2.75V, the POR resets all registers to their default values and the fault is cleared. Bit 6: FST[6]. When the voltage at BMON is above VCC - 0.5V, a SOFT FAULT is reported. Bit 4: FST[4]. When the voltage at BMAX goes above 1.3V, a HARD FAULT is reported. Bit 3: FST[3]. When the common-mode voltage at VTOUTQ goes below VCC - 1.3V, a SOFT FAULT is reported. Bit 2: FST[2]. When the voltage at VTOUTQ goes below VCC - 0.8V, a HARD FAULT is reported. Bit 1: FST[1]. When the BIAS voltage goes below 0.44V, a HARD FAULT is reported. Bit 0: TX_FAULT. Copy of a FAULT signal in FST[7:6] and FST[4:1]. A POR resets the FST bits to 0. Transmitter Status Register 2 (TXSTAT2)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 (STICKY) IMODERR X 2 (STICKY) IBIASERR X 1 (STICKY) TXED X 0 (STICKY) X X ADDRESS H0x07
Bit 3: IMODERR. Any attempt to modify SET_IMOD[8:1] above IMODMAX[7:0] flags a warning at IMODERR. (See the Programming Modulation Current section.) Bit 2: IBIASERR. Any attempt to modify SET_IBIAS[8:1] above IBIASMAX[7:0] flags a warning at IBIASERR. (See the Programming Bias Current section.) Bit 1: TXED. This indicates the absence of an AC signal at the transmit input. Bias Current Setting Register (SET_IBIAS)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x08 SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS [8] (MSB) [7] [6] [5] [4] [3] [2] [1] 0 0 0 0 0 0 0 1
Bits 7 to 0: SET_IBIAS[8:1]. The bias current DAC is controlled by a total of 9 bits. The SET_IBIAS[8:1] bits are used to set the bias current with even denominations from 0 to 510 bits. The LSB (SET_IBIAS[0]) is controlled by the BIASINC register and is used to set the odd denominations in the SET_IBIAS[8:0]. Any direct write to SET_IBIAS[8:1] resets the LSB.
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
Modulation Current Setting Register (SET_IMOD)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x09 SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD [8] (MSB) [7] [6] [5] [4] [3] [2] [1] 0 0 0 0 0 1 0 0
MAX3946
Bits 7 to 0: SET_IMOD[8:1]. The modulation current DAC is controlled by a total of 9 bits. The SET_IMOD[8:1] bits are used to set the modulation current with even denominations from 0 to 510 bits. The LSB (SET_IMOD[0]) is controlled by the MODINC register and is used to set the odd denominations in the SET_IMOD[8:0]. Any direct write to SET_IMOD[8:1] resets the LSB. Maximum Modulation Current Setting Register (IMODMAX)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x0A IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX [7] (MSB) [6] [5] [4] [3] [2] [1] [0] (LSB) 0 0 1 0 0 0 0 0
Bits 7 to 0: IMODMAX[7:0]. The IMODMAX register is an 8-bit register that can be used to limit the maximum modulation current. IMODMAX[7:0] is continuously compared to SET_IMOD[8:1]. Any attempt to modify SET_IMOD[8:1] above IMODMAX[7:0] is ignored and flags a warning at IMODERR. Maximum Bias Current Setting Register (IBIASMAX)
Bit # Name Default Value 7 IBIASMAX [7] (MSB) 0 6 IBIASMAX [6] 0 5 IBIASMAX [5] 1 4 IBIASMAX [4] 0 3 IBIASMAX [3] 0 2 IBIASMAX [2] 0 1 IBIASMAX [1] 0 0 IBIASMAX [0] (LSB) 0 ADDRESS H0x0B
Bits 7 to 0: IBIASMAX[7:0]. The IBIASMAX register is an 8-bit register that can be used to limit the maximum bias current. IBIASMAX[7:0] is continuously compared to SET_IBIAS[8:1]. Any attempt to modify SET_IBIAS[8:1] above IBIASMAX[7:0] is ignored and flags a warning at IBIASERR. Modulation Current Increment Setting Register (MODINC)
Bit # Name Default Value 7 SET_IMOD [0] (LSB) 0 6 X 0 5 X 0 4 MODINC [4] (MSB) 0 3 MODINC [3] 0 2 MODINC [2] 0 1 MODINC [1] 0 0 MODINC [0] (LSB) 0 ADDRESS H0x0C
Bit 7: SET_IMOD[0]. This is the LSB of the SET_IMOD[8:0] bits. This bit can only be updated by the use of MODINC[4:0]. Bits 4 to 0: MODINC[4:0]. This string of bits is used to increment or decrement the modulation current. When written to, the SET_IMOD[8:0] bits are updated. MODINC[4:0] are a two's complement string.
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Bias Current Increment Setting Register (BIASINC)
Bit # Name Default Value 7 SET_IBIAS [0] (LSB) 0 6 X 0 5 X 0 4 BIASINC [4] (MSB) 0 3 BIASINC [3] 0 2 BIASINC [2] 0 1 BIASINC [1] 0 0 BIASINC [0] (LSB) 0 ADDRESS H0x0D
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0]. Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two's complement string. Mode Control Register (MODECTRL)
Bit # Name Default Value 7
MODECTRL [7] (MSB)
6
MODECTRL [6]
5
MODECTRL [5]
4
MODECTRL [4]
3
MODECTRL [3]
2
MODECTRL [2]
1
MODECTRL [1]
0
MODECTRL [0](LSB)
ADDRESS H0x0E
0
0
0
0
0
0
0
0
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables the user to switch between normal and setup modes. The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation. Exceptions are MODINC and BIASINC, which can be updated in normal mode. Pulse-Width Control Register (SET_PWCTRL)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3
[3] (MSB)
2
[2]
1
[1]
0
[0] (LSB)
ADDRESS H0x0F
SET_PWCTRL SET_PWCTRL SET_PWCTRL SET_PWCTRL
0
0
0
0
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width. Deemphasis Control Register (SET_TXDE)
Bit # Name Default Value 7 X X 6 X X 5 4 3 2 1 0 ADDRESS H0x10 SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE [5] (MSB) [4] [3] [2] [1] [0] (LSB) 0 0 0 0 0 1
Bits 5 to 0: SET_TXDE[5:0]. This is a 6-bit register used to control the amount of deemphasis on the transmitter output. When calculating the total modulation current, the amount of deemphasis must be taken into account. The deemphasis is set as a percentage of modulation current. Equalization Control Register (SET_TXEQ)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 X X 2 1 0 X X ADDRESS H0x11 SET_TXEQ SET_TXEQ [2] [1] 0 0
Bits 2 to 1: SET_TXEQ[2:1]. These 2 bits are used to control the amount of equalization on the transmitter input. See Table 1 for more information.
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
Design Procedure
1) IBIASMAX[7:0] = Maximum_Bias_Current_Value 2) SET_IBIASi[8:1] = Initial_Bias_Current_Value Note: The total bias current is calculated using the SET_IBIAS[8:0] DAC value. SET_IBIAS[8:1] are the bits that can be manually written. SET_IBIAS[0] can only be updated using the BIASINC register. When implementing an APC loop it is recommended to use the BIASINC register, which guarantees the fastest bias current update. 3) BIASINCi[4:0] = New_Increment_Value 4) If (SET_IBIASi[8:1] P IBIASMAX[7:0]), then (SET_ IBIASi[8:0] = SET_IBIASi-1[8:0] + BIASINCi[4:0]) 5) Else (SET_IBIASi[8:0] = SET_IBIASi-1[8:0]) The total bias current can be calculated as follows: 6) IBIAS = [SET_IBIASi[8:0] + 16] x 200FA 1) IMODMAX[7:0] = Maximum_Modulation_Current_Value 6b) TXDE_MD[1:0] = 01, then 0.3mA(SET_IMOD[8 : 0] + 16) 50 x IMOD = - 0.15mA(SET_IMOD[8 : 4] + 1) 50 + R LD 6c) TXDE_MD[1:0] = 10, then set SET_TXDE[5:0] can be set to any value SET_IMOD[8:4] and 0.3mA(SET_IMOD[8 : 0] + 16) 50 x IMOD = - 0.15mA(SET_TXDE[5:0] + 1) 50 + R LD When SET_TXDE[5:0] is increased, the deemphasis current increases and the overall peak-to-peak modulation current decreases. This effect saturates when SET_TXDE[5:0] = 0.2 x (SET_IMOD[8:0] + 16) - 1, and further increases to SET_TXDE[5:0] do not increase the deemphasis current. 6d) TXDE_MD[1:0] = 11, then IMOD = 0.9 x 0.3mA(SET_IMOD[8 : 0] + 16) x 50 50 + RLD
MAX3946
Programming Bias Current
Programming Modulation Current
2) SET_IMODi[8:1] = Initial_Modulation_Current_Value x 1.06 Note: The total modulation laser current is calculated using the SET_IMOD[8:0] DAC value, and the SET_TXDE register value. SET_IMOD[8:1] are the bits that can be manually written. SET_IMOD[0] can only be updated using the MODINC register. When implementing modulation compensation, it is recommended to use the MODINC register, which guarantees the fastest modulation current update. 3) MODINCi[4:0] = New_Increment_Value 4) If (SET_IMODi[8:1] P IMODMAX[7:0]), then (SET_ IMODi[8:0] = SET_IMODi-1[8:0] + MODINCi[4:0]) 5) Else (SET_IMODi[8:0] = SET_IMODi-1[8:0]) The following equations give the modulation current (peak-to-peak) seen at the laser when driven differentially. REXTD is the differential load impedance of the laser plus any added series resistance. 6a) TXDE_MD[1:0] = 00, then 0.3mA(SET_IMOD[8 : 0] + 16) 50 x IMOD = 50 + R LD - 0.15mA(SET_IMOD[8 : 3] + 2)
Note: When TXDE_MD[1:0] = 10 and the SET_TXDE register is set by the user, the minimum allowed deemphasis is 3% and the maximum is 10%. These limits are internally set by the MAX3946. 1) TXDE_MD[1:0] = Transmit_Deemphasis_Mode
Programming Transmit Output Deemphasis
2) SET_TXDE[5:0] = Transmit_Deemphasis_Value. If TXDE_MD[1:0] = 00, 01, or 11, the value of SET_TXDE is automatically set by the device and there is no need to enter data to SET_TXDE. For Transmit_Deemphasis_Mode: 00 = deemphasis is fixed at 6% of the modulation amplitude (the device controls the SET_TXDE value), default setting 01 = deemphasis is fixed at 3% of the modulation amplitude (the device controls the SET_TXDE value) 10 = deemphasis is programmed by the SET_TXDE register setting 11 = deemphasis is at its maximum of approximately 9% (the device controls the SET_TXDE value)
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
The eye crossing at the Tx output can be adjusted using the SET_PWCTRL register. Table 5 shows these settings. The sign of the number specifies the direction of
Programming Pulse-Width Control
pulse-width distortion. The code of 1111 corresponds to a balanced state for differential output. The pulse-width distortion is bidirectional around the balanced state (see the Typical Operating Characteristics section).
Table 5. Eye-Crossing Settings for SET_PWCTRL
SET_PWCTRL[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 PWD -7 -6 -5 -4 -3 -2 -1 0 SET_PWCTRL[3:0] 0111 0110 0101 0100 0011 0010 0001 0000 PWD 8 7 6 5 4 3 2 1
Applications Information
Using the MAX3946 laser driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each user must determine the level of fault tolerance required by the application, recognizing that Maxim products are neither designed nor authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application in which the failure of a Maxim product could create a situation where personal injury or death could occur.
Laser Safety and IEC 825
Table 6. Register Summary
REGISTER FUNCTION/ ADDRESS REGISTER NAME NORMAL MODE R R Transmitter Control Register Address = H0x05 R TXCTRL R R R R R R TXSTAT1 R R R SETUP MODE RW RW RW RW RW RW R R R R R R BIT NUMBER/ TYPE 5 4 3 2 1 0 7 (sticky) 6 (sticky) 4 (sticky) 3 (sticky) 2 (sticky) 1 (sticky) BIT NAME TXDE_MD[1] TXDE_MD[0] TXEQ_EN SOFTRES TX_POL TX_EN FST[7] FST[6] FST[4] FST[3] FST[2] FST[1] DEFAULT VALUE 0 0 0 0 1 1 X X X X X X NOTES MSB deemphasis mode LSB deemphasis mode Input equalization 0: disabled, 1: enabled Global digital reset Tx polarity 0: inverse, 1: normal Tx control 0: disabled, 1: enabled TX_PORaTX_VCC lowlimit violation BMON open/shorted to VCC BMAX current exceeded or open/short to ground VTOUT+/- common-mode low-limit VTOUT+/- low-limit violation BIAS open or shorted to ground Copy of FAULT signal in case POR bits 6 to 1 reset to 0
Transmitter Status Register 1 Address = H0x06
R
R
0 (sticky)
TX_FAULT
X
22
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
Table 6. Register Summary (continued)
REGISTER FUNCTION/ ADDRESS Transmitter Status Register 2 Address = H0x07 REGISTER NAME NORMAL MODE R TXSTAT2 R R R R R Bias Current Setting Register Address = H0x08 R SET_IBIAS R R R R SETUP MODE R R R RW RW RW RW RW RW RW RW BIT NUMBER/ TYPE 3 (sticky) 2 (sticky) 1 (sticky) 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 BIT NAME DEFAULT VALUE X X X 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 LSB bias limit 23 LSB modulation limit MSB bias limit LSB modulation DAC MSB modulation limit LSB bias DAC MSB modulation DAC NOTES Warning increment result > IMODMAX Warning increment result > IBIASMAX Tx edge detection MSB bias DAC
MAX3946
IMODERR IBIASERR TXED SET_IBIAS[8] SET_IBIAS[7] SET_IBIAS[6] SET_IBIAS[5] SET_IBIAS[4] SET_IBIAS[3] SET_IBIAS[2] SET_IBIAS[1] SET_IBIAS[0] SET_IMOD[8] SET_IMOD[7] SET_IMOD[6] SET_IMOD[5] SET_IMOD[4] SET_IMOD[3] SET_IMOD[2] SET_IMOD[1] SET_IMOD[0] IMODMAX[7] IMODMAX[6] IMODMAX[5] IMODMAX[4] IMODMAX[3] IMODMAX[2] IMODMAX[1] IMODMAX[0] IBIASMAX[7] IBIASMAX[6] IBIASMAX[5] IBIASMAX[4] IBIASMAX[3] IBIASMAX[2] IBIASMAX[1] IBIASMAX[0]
Accessible through REG_ADDR = H0x0D R R R Modulation Current Setting Register Address = H0x09 R SET_IMOD R R R R RW RW RW RW RW RW RW RW
Accessible through REG_ADDR = H0x0C R Maximum Modulation Current Setting Register Address = H0x0A R R IMODMAX R R R R R R R Maximum Bias Current Setting Register Address = H0x0B R IBIASMAX R R R R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Table 6. Register Summary (continued)
REGISTER FUNCTION/ ADDRESS REGISTER NAME NORMAL MODE R Modulation Current Increment Setting Register Address = H0x0C RW MODINC RW RW RW RW R Bias Current Increment Setting Register Address = H0x0D RW BIASINC RW RW RW RW RW RW Mode Control Register Address = H0x0E RW MODECTRL RW RW RW RW RW Pulse-Width Control Register Address = H0x0F R SET_ PWCTRL R R R R Deemphasis Control Register Address = H0x10 R SET_TXDE R R R R Equalization Control Register Address = H0x11 24 SET_TXEQ R R SETUP MODE R RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT NUMBER/ TYPE 7 4 3 2 1 0 7 4 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 0 5 4 3 2 1 0 2 1 BIT NAME DEFAULT VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 LSB Tx deemphasis Tx equalization LSB Tx pulse-width control MSB Tx deemphasis LSB mode control MSB Tx pulse-width control LSB bias DAC two's complement MSB mode control LSB MOD DAC two's complement LSB of SET_IBIAS DAC register address = H0x08 MSB bias DAC two's complement NOTES LSB of SET_IMOD DAC register address = H0x09 MSB MOD DAC two's complement
SET_IMOD[0] MODINC[4] MODINC[3] MODINC[2] MODINC[1] MODINC[0] SET_IBIAS[0] BIASINC[4] BIASINC[3] BIASINC[2] BIASINC[1] BIASINC[0] MODECTRL[7] MODECTRL[6] MODECTRL[5] MODECTRL[4] MODECTRL[3] MODECTRL[2] MODECTRL[1] MODECTRL[0] SET_PWCTRL[3] SET_PWCTRL[2] SET_PWCTRL[1] SET_PWCTRL[0] SET_TXDE[5] SET_TXDE[4] SET_TXDE[3] SET_TXDE[2] SET_TXDE[1] SET_TXDE[0] SET_TXEQ[2] SET_TXEQ[1]
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
VCCT VCCT DEEMPHASIS CONTROL TIN+ 50I CONTROL LOOP 50I TIN-
25I
25I TOUT+ TOUT-
VCCT
VEET FAULT 7.5kI
VCCD
VEET
VCCD
75kI CLAMP SDA SCL, CSEL 75kI
DISABLE
VEET VEET VEER
VEER
Figure 6. Simplified I/O Structures
The data inputs and outputs are the most critical paths for the device and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the IC: * The data inputs should be wired directly between the cable connector and IC without stubs. * The data transmission lines to the laser should be kept as short as possible and be designed for 50I differential or 25I single-ended characteristic impedance. * An uninterrupted ground plane should be positioned beneath the high-speed I/Os. * Ground path vias should be placed close to the IC and the input/output interfaces to allow a return current path to the IC and the laser.
Layout Considerations
* Maintain 100I differential transmission line impedance into the IC. * Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the schematic and board layers of the MAX3946 Evaluation Kit (MAX3946EVKIT) for more information.
The exposed pad on the 24-pin TQFN provides a very low-thermal resistance path for heat removal from the IC. The pad is also electrical ground on the IC and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information.
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Exposed-Pad Package and Thermal Considerations
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Typical Application Circuit for 10GBASE-LRM
HOST BOARD HOST FILTER VCC SFP CONNECTOR VCC (3.3V) SFP+ OPTICAL TRANSCEIVER SUPPLY FILTER
VCCD ZDIFF = 100I 0.1F TIN+ TINFR4 MICROSTRIP UP TO 5.5in 0.1F
VCCT TOUT-
TOUT+ BIAS 10G FP-TOSA
MAX3946
BMAX BMON 3-WIRE INTERFACE FAULT DISABLE VEET VCC SCL SDA CSEL R1 R2
4.7kI TO 10kI SerDes TX_FAULT TX_DISABLE RATE SELECT MODE_DEF1 (SCL) MODE_DEF2 (SDA) VCC HOST FILTER ZDIFF = 100I
DS1878 SFP CONTROLLER
SOFTWARE 3-WIRE INTERFACE
I2C
ADC RPD
VCC (3.3V) 0.1F
10G LINEAR PIN ROSA SUPPLY FILTER
FR4 MICROSTRIP UP TO 12in
0.1F
RMON
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance
Typical Application Circuit for 10GBASE-LR
HOST BOARD HOST FILTER VCC SFP CONNECTOR VCC (3.3V) SFP+ OPTICAL TRANSCEIVER SUPPLY FILTER
MAX3946
VCCD ZDIFF = 100I 0.1F TIN+ TINFR4 MICROSTRIP UP TO 5.5in 0.1F
VCCT TOUT-
TOUT+ BIAS 10G DFBTOSA R2
MAX3946
11.3G FP/DFB LDD BMAX BMON 3-WIRE INTERFACE FAULT DISABLE VEET VCC SCL SDA CSEL
R1
4.7kI TO 10kI SerDes TX_FAULT RATE SELECT TX_DISABLE MODE_DEF1 (SCL) MODE_DEF2 (SDA) VCC HOST FILTER VCC (3.3V) SUPPLY FILTER VCCR VCC CAZ 3-WIRE INTERFACE SCL SDA CSEL RPMIN LOS ZDIFF = 100I 0.1F ROUT+ ROUTFR4 MICROSTRIP UP TO 12in 0.1F VEE 10G PIN ROSA LOS
DS1878 SFP CONTROLLER
SOFTWARE 3-WIRE INTERFACE
I2C
ADC RPD
4.7kI TO 10kI
MAX3945 11.3G LAM
0.1F RIN+ RIN0.1F RMON
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946
Chip Information
PROCESS: SiGe BiPOLAR
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 TQFN-EP PACKAGE CODE T2444+3 DOCUMENT NO. 21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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